1. Field of the Invention
The present invention relates to semiconductor devices, in particular, to input/output (I/O) buffers in semiconductor devices.
2. Description of the Related Art
Semiconductor devices are often manufactured on silicon wafers. As a consequence, a transistor's electrical characteristics vary on the semiconductor according to a variety of factors. Factors affecting the electrical characteristics of a transistor include the direction orientation of its gate and its location relative to other transistors. As semiconductor manufacturing advances using microprocessor technologies, characteristic variations of transistors due to varying orientation of the transistors increasingly affect overall semiconductor performance. For example, many complementary metal oxide semiconductor (CMOS) technologies (e.g., 28 nm technologies) have restrictions on the layout of low voltage transistors.
Semiconductor devices typically include at least one input/output (I/O) circuit in an I/O buffer enabling communication with other devices. The I/O buffers are generally disposed along four sides of an integrated circuit (IC) chip's core area, forming an I/O ring that surrounds the core. The semiconductor's core is where logical computations are made. The I/O buffers on the two sides of the I/O ring typically have a perpendicular orientation to the I/O buffers on the top and bottom of the ring. The orientation of the I/O buffers on the top and bottom might be referred to as a standard orientation, and the orientation of the I/O buffers on the sides might be referred to as a rotated orientation. The I/O buffers on the sides of the I/O ring might be laid out the same as the top and bottom I/O buffers, but then they are rotated 90 degrees.
I/O buffers employ voltage translators to interface between off-chip supply voltages and lower core-logic voltages. The voltage translators often employ low voltage transistors with narrow gates, and the transistors' performance characteristics, such as timing, are highly dependent upon their orientation. For example, some CMOS technologies require all narrow length, low voltage transistor gates to be oriented in the same direction in a chip and a wafer. Rotating a low voltage gate 90 degrees in an I/O buffer, as is common practice, alters device performance and timing in CMOS technologies that are highly dependent on layout topological design. A separate, rotated layout for the I/O buffers that occupy the sides of the ring might ensure all translator circuits with low voltage devices are oriented in the same direction. However, this practice is inefficient and the different features of the two layouts affect performance of the translator and the I/O buffers. Other approaches, as described in United States Patent Publication No. 2010/0096670 filed on Dec. 18, 2009, do not rotate the I/O buffers, and thus all I/O buffers have the same orientation.